/* ===========================================================================
	2009  Robert C Fingh

	WXGASyncGen840x1050_60Hz.v
		WXGA sync generator

	This source code is available only for veiwing, testing and evaluation
	purposes. Any commercial use requires a license. This copyright
	statement and disclaimer must remain present in the file.

	NO WARRANTY.
    THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
	EXPRESS OR IMPLIED. The user must assume the entire risk of using the
	Work.

	IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
    INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
    THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.

	IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
	IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
	REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
	LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
	AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
	LOSSES RELATING TO SUCH UNAUTHORIZED USE.


	VGA video sync generator.

	Input clock:     73.529 MHz (50 MHz * 25/17)
	Horizontal freq: 65.186 kHz	(generated)
	Vertical freq:   59.968  Hz (generated)

	This module generates the basic sync timing signals required for a
	WXGA display.

	Note to self
	Webpack 9.2i  xc3s1200e-4fg320
	32 FF's / 49 slices / 90 LUTs / 144.217 MHz (speed Spartan3e-4)
============================================================================ */

module WXGASyncGen840x1050_60Hz(rst, clk, hSync, vSync, blank, border, eol, eof);
// 147.136320 MHz
// 73.56816 Mhz
// 73.529412 MHz actual 50 * 25/17
	parameter phSyncOn  = 48;		//   48 front porch
	parameter phSyncOff = 136;		//   92 sync
	parameter phBlankOff = 280;		//  144 back porch
	parameter phBorderOff = 284;	//    4 border
	parameter phBorderOn = 1124;	//  840 display
	parameter phBlankOn = 1128;		//    4 border
	parameter phTotal = 1128;		// 1128 total clocks
// 65220 = 60 * 1088 kHz
	parameter pvSyncOn  = 1;		//    1 front porch
	parameter pvSyncOff = 4;		//    3 vertical sync
	parameter pvBlankOff = 34;		//   30 back porch
	parameter pvBorderOff = 36;		//    2 border
	parameter pvBorderOn = 1086;	// 1050 display
	parameter pvBlankOn = 1087;  	//    1 border
	parameter pvTotal = 1087;		// 1087 total scan lines
// 60 Hz
// 840x1050
	input rst;			// reset
	input clk;			// video clock
	output hSync, vSync;	// sync outputs
	output blank;			// blanking output
	output border;
	output eol;			// end of line
	output eof;			// end of frame

	//---------------------------------------------------------------------
	//---------------------------------------------------------------------

	wire [11:0] hCtr;	// count from 1 to 2256
	wire [11:0] vCtr;	// count from 1 to 1087

	wire vBlank, hBlank;
	reg blank;
	reg border;

	assign eol     = hCtr == phTotal;
	wire hSyncOn   = hCtr == phSyncOn;
	wire hSyncOff  = hCtr == phSyncOff;
	wire hBorderOn = hCtr == phBorderOn;
	wire hBorderOff= hCtr == phBorderOff;
	wire hBlankOn  = hCtr == phBlankOn;
	wire hBlankOff = hCtr == phBlankOff;

	assign eof     = vCtr == pvTotal && eol;
	wire vSyncOn   = vCtr == pvSyncOn;
	wire vSyncOff  = vCtr == pvSyncOff;
	wire vBorderOn = vCtr == pvBorderOn;
	wire vBorderOff= vCtr == pvBorderOff;
	wire vBlankOn  = vCtr == pvBlankOn;
	wire vBlankOff = vCtr == pvBlankOff;

	counter #(12) u1 (.rst(rst), .clk(clk), .ce(1'b1), .ld(eol), .d(12'd1), .q(hCtr) );
	counter #(12) u2 (.rst(rst), .clk(clk), .ce(eol),  .ld(eof), .d(12'd1), .q(vCtr) );

	sc_flipflop u3 (.rst(rst), .clk(clk), .set(hBlankOn),  .clr(hBlankOff),  .o(hBlank) );
	sc_flipflop u4 (.rst(rst), .clk(clk), .set(vBlankOn),  .clr(vBlankOff),  .o(vBlank) );
	sc_flipflop u5 (.rst(rst), .clk(clk), .set(hSyncOff),  .clr(hSyncOn),    .o(hSync) );	// -ve hsync
	sc_flipflop u6 (.rst(rst), .clk(clk), .set(vSyncOn),   .clr(vSyncOff),   .o(vSync) );	// +ve vsync
	sc_flipflop u7 (.rst(rst), .clk(clk), .set(hBorderOn), .clr(hBorderOff), .o(hBorder) );
	sc_flipflop u8 (.rst(rst), .clk(clk), .set(vBorderOn), .clr(vBorderOff), .o(vBorder) );

    always @(posedge clk)
        blank <= hBlank|vBlank;
    always @(posedge clk)
        border <= hBorder|vBorder;

endmodule