/* ============================================================================
	(C) 2007  Robert T Finch
	All rights reserved.
	rob@birdcomputer.ca

	VT612.v
		74LS612 similar memory mapper.


    This source code is available for evaluation and validation purposes
    only. This copyright statement and disclaimer must remain present in
    the file.


	NO WARRANTY.
    THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
    EXPRESS OR IMPLIED. The user must assume the entire risk of using the
    Work.

    IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
    INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
    THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.

    IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
    IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
    REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
    LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
    AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
    LOSSES RELATING TO SUCH UNAUTHORIZED USE.


    Notes:

   	Verilog 1995
   	Ref: Webpack9.2 xc3s1000-4ft256
	20 slices / 38 LUTs / 10.53 ns
============================================================================ */

module VT612(clk_i, cyc_i, stb_i, we_i, ack_o, adr_i, dat_i, dat_o, mm, me, ma, mo);
	// Syscon
	input clk_i;		// clock
	// Bus slave interface
	input cyc_i;		// cycle valid
	input stb_i;		// strobe
	output ack_o;		// transfer acknowledged
	input we_i;			// write enable
	input [3:0] adr_i;	// register select
	input [11:0] dat_i;
	output [11:0] dat_o;
	// 
	input mm;			// mapped mode: 1=unmapped,0=mapped
	input me;			// map output enable - active low (LS612 is active low)
	input [3:0] ma;		// address bits to map
	output [11:0] mo;	// mapped address
	tri [11:0] mo;

	assign ack_o = cyc_i & stb_i;

	reg [11:0] mem [15:0];

	always @(posedge clk_i)
		if (cyc_i & stb_i & we_i)
			mem[adr_i] <= dat_i;

	assign dat_o = mem[adr_i];
	assign mo = me ? 12'bz : mm ? {8'b0,ma} : mem[ma];	// LS612 is {ma,8'b0}

endmodule