/* ============================================================================
	(C) 2007  Robert T Finch
	All rights reserved.
	rob@birdcomputer.ca

	updown_counter.v
		Counts either up or down.


    This source code is available for evaluation and validation purposes
    only. This copyright statement and disclaimer must remain present in
    the file.


	NO WARRANTY.
    THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
    EXPRESS OR IMPLIED. The user must assume the entire risk of using the
    Work.

    IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
    INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
    THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.

    IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
    IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
    REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
    LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
    AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
    LOSSES RELATING TO SUCH UNAUTHORIZED USE.


    Notes:
    Incrementing and decrementing at the same time results in no change.

   	Verilog 1995
   	8 bits
   	Ref: Webpack9.2 xc3s1000-4ft256
	12 slices / 22 LUTs / 176.772 MHz
============================================================================ */

module updown_counter(rst, clk, ce, inc, dec, ld, tgt, d, q, tc);
	parameter WID=8;
	input rst;				// reset
	input clk;				// clock
	input ce;				// count enable
	input inc;				// increment
	input dec;				// decrement
	input ld;				// load
	input [WID:1] tgt;		// target count
	input [WID:1] d;		// value to load
	output [WID:1] q;		// current value
	output tc;				// true when target count is reached

	reg [WID:1] q;
	assign tc = q == tgt;

	wire [WID:1] amt = {{WID-1{dec & ~inc}},{inc^dec}};

	always @(posedge clk)
		if (rst)
			q <= 0;
		else if (ld)
			q <= d;
		else if (ce)
			q <= q + amt;

endmodule