/* ===============================================================
	(C) 2006  Robert Finch
	All rights reserved.
	rob@birdcomputer.ca


	rol.v


	This source code is free for use and modification for
	non-commercial or evaluation purposes, provided this
	copyright statement and disclaimer remains present in
	the file.

	If the code is modified, please state the origin and
	note that the code has been modified.

	NO WARRANTY.
	THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF
	ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume
	the entire risk of using the Work.

	IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
	ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES
	WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR
	RELATIONSHIP WITH THE AUTHOR.

	IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU
	TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE
	WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED
	TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS
	OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK,
	AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS
	FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED
	USE.
	


	Rotate or shift left by 0 to 63 bits.
	Parameterized with a default width of 32 bits.
	- non-clocked (single cycle)
	- combinational logic

	Resource Usage Samples (32 bits):
	Ref. SpartanII
	162 LUTs

	Webpack 7.1i xc3s1000-4ft256
	184LUTs / 94 slices / 16ns
=============================================================== */

// op
//	0	shift left
//	1	rotate left
module rol
#(parameter WID = 32)
(
	input op,
	input [WID:1] a,
	input [5:0] b,
	output [WID:1] o
);
	wire [WID:1] t1, t2, t3;
	assign o = t3;

	rolx1  #(WID) u1 (op,  a, b[1:0], t1);
	rolx4  #(WID) u2 (op, t1, b[3:2], t2);
	rolx16 #(WID) u3 (op, t2, b[5:4], t3);

endmodule