/* ============================================================================
	(C) 2005-2007  Robert T Finch
	All rights reserved.
	rob@birdcomputer.ca


	overflow.v

	Verilog 1995

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	This module computes overflow for add/subtract given two operands and the
	result. Assuming we don't know what the carry input is and there may
	have been one.
============================================================================ */

module overflow(op, a, b, s, v);

	input op;	// 0=add,1=sub
	input a;
	input b;
	input s;	// sum
	output v;

	// Overflow:
	// Add: the signs of the inputs are the same, and the sign of the
	// sum is different
	// Sub: the signs of the inputs are different, and the sign of
	// the sum is the same as B
	assign v = (op ^ s ^ b) & (~op ^ a ^ b);

endmodule