/* ============================================================================
	(C) 2007  Robert T Finch
	All rights reserved.
	rob@birdcomputer.ca

	critical_reset_gen.v

	Verilog 1995

    This source code is available for evaluation and validation purposes
    only. This copyright statement and disclaimer must remain present in
    the file.


	NO WARRANTY.
    THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
    EXPRESS OR IMPLIED. The user must assume the entire risk of using the
    Work.

    IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
    INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
    THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.

    IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
    IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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	    Critical reset signal generator.
	    Holds the creset signal high until DELAY cycles
	after rst goes low.
	
	2 slices / 246 MHz
============================================================================ */

module critical_reset_gen(clk, rst, creset);
	parameter pDelay = 8;	// 15 cycles max
    input clk;
    input rst;
    output creset;

	reg [3:0] cnt;
	assign creset = |cnt;

	always @(posedge clk)
		if (rst)
			cnt <= pDelay;
		else if (creset)
			cnt <= cnt - 1;

endmodule