/* ===============================================================
	(C) 2004  Bird Computer
	All rights reserved.

	clk60Hz.v
	Version 1.0

	50/60Hz clock pulse generator
	
		Please read the Licensing Agreement	(license.html file).
	Use of this file is subject to the license agreement.

	You are free to use and modify this code for non-commercial
	or evaluation purposes.
	
	If you do modify the code, please state the origin and
	note that you have modified the code.

	This source file may be used without restriction, but not
	distributed, provided this copyright statement remains
	present in the file. Any derivative work must also
	contain the original copyright notice and the following
	disclaimer.


	NO WARRANTY.
	THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF
	ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume
	the entire risk of using the Work.

	IN NO EVENT SHALL BIRD COMPUTER OR ITS PRINCIPALS OR
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		This function is probably better done using an LFSR.
	But you'd have to build a custom LFSR for a given clock
	frequency and output frequency. This core is easy to use
	at a cost of some extra hardware. It can actually be
	used for more than 50/60Hz clock generation as the
	frequencies are parameterized.
================================================================ */

module clk60Hz(rst, clk, ce, clk60);
	parameter pClkFreq = 20000000;
	parameter pOutFreq = 60;
	parameter pCounterBits = 31;
	localparam pMaxCount = 1 << pCounterBits;
	localparam pClkMul = pMaxCount / (pClkFreq / pOutFreq);
	input rst;
	input clk;
	input ce;
	output clk60;

	reg [pCounterBits:0] c;	// current count
	reg pcmsb;				// previous value of count msb

	wire clk60 = c[pCounterBits] & ~pcmsb;	// edge detector (active one cycle only!)

	always @(posedge clk)
		if (rst) begin
			c <= {pCounterBits{1'b0}};
			pcmsb <= 1'b0;
		end
		else if (ce) begin
			c <= c + pClkMul;
			// for detecting an edge on the msb
			pcmsb <= c[pCounterBits];
		end


endmodule